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1 date: 9/13/04 sp6123 low voltage, synchronous step down pwm controller ?copyright 2004 sipex corporation sp6123/sp6123a optimized for single supply, 3v - 5.5v applications high efficiency: greater than 95% possible accurate fixed 300khz (sp6123) or 500khz (sp6123a) frequency operation fast transient response internal soft start circuit accurate 0.8v reference allows low output voltages resistor programmable output voltage loss-less current limit with high side r ds(on) sensing hiccup mode current limit protection dual n-channel mosfet synchronous driver quiescent current: 500 a, 30 a in shutdown 8-pin surface mount package low voltage, synchronous step-down pwm controller ideal for 2a to 10a, small footprint, dc-dc power converters applications dsp microprocessor core i/o & logic industrial control distributed power low voltage power the sp6123 is a fixed frequency, voltage mode, synchronous pwm controller designed to work from a single 5v or 3.3v input supply, providing excellent ac and dc regulation for high efficiency power conversion. requiring only few external components, the sp6123 pack- aged in an 8-pin nsoic, is especially suited for low voltage applications where cost, small size and high efficiency are critical. the operating frequency is internally set to 300khz (sp6123) or 500khz (sp6123a), allowing small inductor values and minimizing pc board space. the sp6123 drives an all n-channel synchronous power mosfet stage for improved efficiency and includes an accurate 0.8v reference for low output voltage applications. typical application circuit bst swn v cc v fb comp gh gl gnd cc 4.7nf rz 15k cb 2.2 f v in sp6123a cp 56pf fds6890a c in 680 f r1 10k v out in 0.8v to 5.0v 2a to 10a (1.6v, 4a shown) cbst 1 f mbr0530 l1 1.5 h fds6890a c out1 470 f c out3 1 f r2 10k c out2 470 f stps2l25u 3v to 5.5v now available in lead free packaging description 1 2 3 4 5 6 7 8 sp6123 8 pin nsoic comp gl bst gh swn v fb v cc gnd features
2 date: 9/13/04 sp6123 low voltage, synchronous step down pwm controller ?copyright 2004 sipex corporation parameter min typ max units conditions quiescent current v cc supply current 0.5 1.0 ma no switching v cc supply current (disabled) 30 60 a comp = 0v error amplifier error amplifier transconductance 0.6 ms comp sink current 15 35 60 av fb = 0.9v, comp = 0.9v, no faults comp source current 15 35 60 av fb = 0.7v, comp = 2v comp output impedance 3 m ? v fb input bias current 100 na error amplifier reference 0.788 0.8 0.812 v trimmed with error amp in unity gain oscillator & delay path internal oscillator frequency 270 300 330 khz sp6123 internal oscillator frequency 450 500 550 khz sp6123a max. controlled duty cycle 90 93 % minimum duty cycle 0 % comp=0.7v minimum gh pulse width 100 250 ns v cc > 4.5v, ramp up comp voltage until gh starts switching current limit internal current limit threshold 160 200 240 mv v cc - v swn ; temp = 25 c; v bst - v cc > 2.5v current limit threshold 0.34 %/c temperature coefficient current limit time constant 15 us soft start, shutdown, uvlo internal soft start slew rate sp6123a 0.2 0.60 0.95 v/ms sp6123 0.1 0.3 0.6 v/ms comp discharge current 185 a comp = 0.5v, fault initiated comp clamp voltage 0.55 0.65 0.75 v v fb = 0.9v comp clamp current 10 30 65 a comp = 0.5v, v fb = 0.9v shutdown threshold voltage 0.29 0.34 0.39 v measured at comp pin shutdown input pull-up current 2 5 10 a comp = 0.2v, measured at comp pin v cc start threshold 2.63 2.8 2.95 v v cc stop threshold 2.47 2.7 2.9 v unless otherwise specified: 0 c < t a < 70 c, 3.0v < v cc < 5.5v, c comp = 22nf, cgh = cgl = 3.3nf, v fb = 0.8v, swn = gnd=0v, typical value for design guideline only. absolute maximum ratings these are stress ratings only and functional operation of the device at these ratings or any other above those indicated in the operation sections of the specifications below is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. v cc ....................................................................................................... 7v bst .................................................................. 13.2v bs t- swn .............................................................. 7v all other pins ................................ -0.3v to v cc + 0.3v peak output current < 10 s gh,gl .................................................................. 2a storage temperature ........................ -65 c to 150 c power dissipation lead temperature (soldering, 10 sec) ............ 300 c esd rating. ................................................ 2kv hbm electrical characteristics
3 date: 9/13/04 sp6123 low voltage, synchronous step down pwm controller ?copyright 2004 sipex corporation pin description pin n0. pin name description 1g l high current driver output for the low side mosfet switch. it is always low if gh is high. gl swings from gnd to v cc . 2v cc positive input supply for the control circuitry and the low side gate driver. properly bypass this pin to gnd with a low esl/esr ceramic capacitor. 3 gnd ground pin. both power and control circuitry of the ic is referenced to this pin. 4 comp output of the error amplifier. it is internally connected to the non-inverting input of the pwm comparator. a lead-lag network is typically connected to the comp pinto compen- sate the feedback loop in order to optimize the dynamic performance of the voltage mode control loop. sleep mode can be invoked by pulling the comp pin below 0.3v with an external open-drain or open-collector transistor. supply current is reduced to 30 a (typical) in shutdown. an internal 5 a pull-up ensures start-up. 5v fb feedback voltage pin. it is the inverting input of the error amplifier and serves as the output voltage feedback point for the buck converter. the output voltage is sensed and can be adjusted through an external resistor divider. 6 swn lower supply rail for the gh high-side gate driver. it also connects to the current limit comparator. connect this pin to the switching node at the junction between the two external power mosfet transistors. this pin monitors the voltage drop across the r ds(on) of the high side n-channel mosfet while it is conducting. when this drop exceeds the internal 200mv threshold, the overcurrent comparator sets the fault latch and terminates the output pulses. the controller stops switching and goes through a hiccup sequence. this prevents excessive power dissipation in the external power mosfets during an overload condition. an internal delay circuit prevents that very short and mild overload conditions, that could occur during a load transient, from activating the current limit circuit. 7g h high current driver output for the high side mosfet switch. it is always low if gl is high or during a fault. gh swings from swn to bst. 8 bst high side driver supply pin. connect bst to the external boost diode and capacitor as shown in the application schematic of page #1. voltage between bst and swn should not exceed 5.5v. unless otherwise specified: 0 c < t a < 70 c, 3.0v < v cc < 5.5v, c comp = 22nf, cgh = cgl = 3.3nf, v fb = 0.8v, swn = gnd=0v, typical value for design guideline only. parameter min typ max units conditions gate drivers gh rise time 110 ns v cc > 4.5v gh fall time 110 ns v cc > 4.5v gl rise time 110 ns v cc > 4.5v gl fall time 110 ns v cc > 4.5v gh to gl non-overlap time 100 ns v cc > 4.5v gl to gh non-overlap time 100 ns v cc > 4.5v electrical characteristics
4 date: 9/13/04 sp6123 low voltage, synchronous step down pwm controller ?copyright 2004 sipex corporation general overview the sp6123 is a constant frequency, voltage mode, synchronous pwm controller designed for low voltage, dc/dc step down converters. it is in- tended to provide complete control for a high power, high efficiency, precisely regulated output voltage from a highly integrated 8-pin solution. the internal free-running oscillator accurately sets the pwm frequency at 300khz or 500khz without requiring any external elements and allows the use of physically small, low value external compo- nents without compromising performance. a transconductance amplifier is used for the error amplifier, which compares an attenuated sample of the output voltage with a precision, 0.8v refer- ence voltage. the output of the error amplifier (comp), is compared to a 0.75v peak-to-peak ramp waveform to provide pwm control. the comp pin provides access to the output of the error amplifier and allows the use of external components to stabilize the voltage loop. high efficiency is obtained through the use of synchronous rectification. synchronous regula- tors replace the catch diode in the standard buck converter with a low r ds(on) n-channel mosfet switch allowing for significant effi- ciency improvements. the sp6123 includes two fast mosfet drivers with internal non-overlap circuitry and drives a pair of n-channel power transistors. the sp6123 includes an internal soft-start circuit that provides controlled ramp up of the output voltage, preventing overshoot and inrush current at power up. current limiting is implemented by monitoring the voltage drop across the r ds(on) of the high side n-channel mosfet while it is conducting, thereby eliminating the need for an external sense resistor. the overcurrent comparator has a built-in threshold of 200mv . when the overcurrent threshold is exceeded, the overcurrent comparator sets the fault latch and terminates the output pulses. the controller stops switching and goes through a hiccup se- quence. this prevents excessive power dissipa- tion in the external power mosfets during an overload condition. an internal delay circuit prevents that very short and mild overload con- ditions, that could occur during a load transient, activate the current limit circuit. + - - + - + synchronous driver pwm logic s q r reset dominant r q s v cc swn reference 4 5 0.8v uvlo f ault swn 6 1 gl 7 driver enable reset dominant pwm comp f ault + - x 2.5 gh gh 5 a 350mv shutdown gm error amp over current (gated s&h) 2.8v on 2.7v off comp shutdown f = 300khz; sp6123 f = 500khz; sp6123a 750mv ramp softstart v fb comp 2 - + - + 1v 500mv (4000 ppm/ c) + - gnd 3 8 bst block diagram operation
5 date: 9/13/04 sp6123 low voltage, synchronous step down pwm controller ?copyright 2004 sipex corporation a low power sleep mode can be invoked in the sp6123 by externally forcing the comp pin below 0.3v. quiescent supply current in sleep mode is typically less than 30 a. an internal 5 a pull-up current at the comp pin brings the sp6123 out of shutdown mode. an internal 0.8v 1.5% reference allows output voltage adjustment for low voltage applications. the sp6123 also includes an accurate under- voltage lockout that shuts down the controller when the input voltage falls below 2.7v. output overvoltage protection is achieved by turning off the high side switch and turning on the low side n-channel mosfet 100% of the time. enable low quiescent mode or ?leep mode?is initi- ated by pulling the comp pin below 0.3v with an external open-drain or open-collector tran- sistor. supply current is reduced to 30 a (typi- cal) in shutdown. on power-up, assuming that vcc has exceeded the uvlo start threshold (2.8v), an internal 5 a pull-up current at the comp pin brings the sp6123 out of shutdown mode and ensures start-up. during normal oper- ating conditions and in absence of a fault, an internal clamp prevents the comp pin from swinging below 0.6v. this guarantees that dur- ing mild transient conditions, due either to line or load variations, the sp6123 does not enter shutdown unless it is externally activated. during sleep mode, the high side and low side mosfets are turned off and the internal soft start voltage is held low. uvlo assuming that there is not shutdown condition present, then the voltage on the v cc pin deter- mines operation of the sp6123. as v cc rises, the uvlo block monitors v cc and keeps the high side and low side mosfets off and the internal ss voltage low until v cc reaches 2.8v. if no faults are present, the sp6123 will initiate a soft start when v cc exceeds 2.8 v. hysteresis (about 100mv) in the uvlo com- parator provides noise immunity at start-up. soft start soft start is required on step-down controllers to prevent excess inrush current through the power train during start-up. typically this is managed by sourcing a controlled current into a timing capacitor and then using the voltage across this capacitor to slowly ramp up either the error amp reference or the error amp output (comp). the control loop creates narrow width driver pulses while the output voltage is low and allows these pulses to increase to their steady-state duty cycle as the output voltage increases to its regu- lated value. as a result of controlling the induc- tor volt*second product during startup, inrush current is also controlled. in the sp6123 the duration of the soft-start is controlled by an internal timing circuit that provides a 0.27v/ms slew-rate, which is used during startup and overcurrent to set the hiccup time. the sp6123 implements soft-start by ramp- ing up the error amplifier reference voltage providing a controlled slew-rate of the output voltage, thereby preventing overshoot and in- rush current at power up. the presence of the output capacitor creates extra current draw during startup. simply stated, dv out /dt requires an average sustained current in the output capacitor and this current must be considered while calculating peak inrush cur- rent and over current thresholds. an approxi- mate expression to determine the excess inrush current due to the dv out /dt of the output capaci- tor c out is: iinrush = c out x s ss x v out 0.8v where, s ss = softstart slew rate, 0.6v/ms for sp6123a and 0.3v/ms for sp6123. as the figure shows, the ss voltage controls a variety of signals. first, provided all the exter- nal fault conditions are removed, an internal 5 a pull-up at the comp pin brings the sp6123 out of shutdown mode. the internal timing circuit is then activated and controls the ramp- up of the error amp reference voltage. the comp pin is pulled to 0.7v by the internal operation: continued operation
6 date: 9/13/04 sp6123 low voltage, synchronous step down pwm controller ?copyright 2004 sipex corporation clamp and then gradually charges preventing the error amplifier from forcing the loop to maximum duty cycle. as the comp voltage crosses about 1v (valley voltage of the pwm ramp), the driver begins to switch the high side mosfet with narrow pulses in an effort to keep the converter output regulated . the sp6123 operates at low duty cycle as the comp voltage increases above 1v. as the error amp reference ramps upward, the driver pulses widen until a steady state value is reached and the output voltage is regulated to the final value ending the soft start charge cycle. hiccup mode when the converter enters a fault mode, the sp6123 holds the high side and low side mosfets off for a finite period of time. pro- vided that the sp6123 is enabled, this time is set by the internal charge of the soft-start capacitor. in the event of an overcurrent condition, the current sense comparator sets the fault latch, which in turn discharge the internal ss capaci- tor, the comp pin and holds the output drivers off. during this condition, the sp6123 stays off for the time it takes to discharge the comp pin down to the 0.27v shutdown threshold. at this point, the fault latch is reset, but before the sp6123 is allowed to attempt restart, the comp pin has to charge back to 1v before any output switching can be initiated. then, the regulator attempts to restart normally by delivering short gate pulses and if the overcurrent condition is still present, the cycle will repeat itself. how- ever, if upon restart, the overcurrent condition is still present, the sp6123 will detect the fault and remain in a fault state until comp reaches about v cc -1v thereby increasing the mosfet off- time. this protection scheme minimizes ther- mal stress to the regulator components as the overcurrent condition persists. the simplified waveforms that describe the hic- cup mode operation are shown below. 200 mv 3 v 0.3 v v comp 1.0 v gh v swn v bst v cc -v swn v oltage time 0 v 0.8 v i(l) time 0.3 v 0.7 v 1 v 0 v v out = v ref * (1+r1/r2) comp internal ss 0 v swn vo ltage vo ltage faul t current inductor 0 a vo ltage reference error amp 0 v v(v cc ) 0 v v(v cc ) operation
7 date: 9/13/04 sp6123 low voltage, synchronous step down pwm controller ?copyright 2004 sipex corporation a more detailed description of the waveform is shown below. internal sstart p asses v(v fb ), comp pops to ~ internal sstart voltage +0.7v internal sstart rises until ~ v cc -1v, then gives command to attempt restart comp clamps ~ 3v after pop, comp retains internal sstart slope enable part a ttempt restart 5 a pullup slope to 0.3v; 35 a pullup to 0.7v overcurrent detected g h turns off (fault mode enabled) g h comp sp6123 over current (hiccup mode) test conditions v fb = 0.7v v cc = 5.0v bst = 5.0v swn - tied to gnd through 1k resistor comp ?released from gnd operation
8 date: 9/13/04 sp6123 low voltage, synchronous step down pwm controller ?copyright 2004 sipex corporation - v(diode) v ~ 0 v 5 v non-overlap gh(gl) 10 % 90 % f all time 2 v gl(gh) 10 % 90 % rise time 5 v 2 v gate driver test conditions time ~ 2*v(vin) ~ v(vin) bst v oltage swn v(vcc=vin) v oltage v oltage v oltage v(bst) gl gh v(vcc) 0 v 0 v over current protection over current protection on the sp6123 is imple- mented through detection of an excess voltage condition across the high side nmos switch dur- ing conduction. this is typically referred to as high side r ds(on) detection and eliminates the need of an external sense resistor. the over current com- parator charges an internal sampling capacitor each time v(v cc )-v(swn) exceeds the 200mv (typ) internal threshold and the gh voltage is high. the discharge/charge current ratio on the sam- pling capacitor is about 2%. therefore, provided that the over current condition persists, the capaci- tor voltage will be pumped up during each time gh switches high. this voltage will trigger an over current condition upon reaching a cmos inverter threshold. there are many advantages to this approach. first, the filtering action of the gated scheme protects against false and undesirable trig- gering that could occur during a minor transient overload condition or supply line noise. further- more, the total amount of time to trigger the fault depends on the on-time of the high side nmos switch. fifteen, 1 s pulses are equivalent to thirty, 500ns pulses or one, 15 s pulse, however, depend- ing on the period, each scenario takes a different amount of total time to trigger a fault. therefore, the fault becomes an indicator of average power in the high side switch. the 200mv overcurrent threshold has a 3400 ppm/ c temperature coeffi- cients in an effort to first order match the thermal characteristics of the r ds(on) of the high side nmos switch. it assumed that the sp6123 will be used in compact designs where there is a high amount of thermal coupling between the high side switch and the controller. output drivers the sp6123, unlike some other bipolar control- ler ic?, incorporates gate drivers with rail-to- rail swing that help prevent spurious turn on due to capacitive coupling. the driver stage consists of one high side nmos, 4 ? driver, gh, and one low side, 4 ? , nmos driver, gl, optimized for driving external power mosfet? in a syn- chronous buck topology. the output drivers also provide gate drive non-overlap mechanism that provides a dead time between gh and gl transitions to avoid potential shoot-through prob- lems in the external mosfets. the following figure shows typical waveforms for the output drivers. as with all synchronous designs, care must be taken to ensure that the mosfets are properly chosen for non-overlap time, enhancement gate drive voltage, ?n?resistance r ds(on) , reverse transfer capacitance crss, input voltage and maximum output current. operation
9 date: 9/13/04 sp6123 low voltage, synchronous step down pwm controller ?copyright 2004 sipex corporation inductor selection there are many factors to consider in selecting the inductor including cost, efficiency, size and emi. in a typical sp6123 circuit, the inductor is chosen primarily for value, saturation current and dc resistance. increasing the inductor value will decrease output voltage ripple, but degrade transient response. low inductor values provide the smallest size, but cause large ripple currents, poor efficiency and more output capacitance to smooth out the larger ripple current. the induc- tor must also be able to handle the peak current at the switching frequency without saturating, and the copper resistance in the winding should be kept as low as possible to minimize resistive power loss. a good compromise between size, loss and cost is to set the inductor ripple current to be within 20% to 40% of the maximum output current. the switching frequency and the inductor oper- ating point determine the inductor value as fol- lows: (max) (max) (max) ) ( out r s in out in out i k f v v v v l ? = where: f s = switching frequency k r = ratio of the peak to peak inductor ripple current to the maximum output current the peak to peak inductor ripple current is: l f v v v v i s in out in out pp (max) (max) ) ( ? = once the required inductor value is selected, the proper selection of core material is based on peak inductor current and efficiency require- ments. the core material must be large enough not to saturate at the peak inductor current 2 (max) pp out peak i i i + = and provide low core loss at the high switching frequency. low cost powdered iron cores have a gradual saturation characteristic but can intro- duce considerable ac core loss, especially when the inductor value is relatively low and the ripple current is high. ferrite materials, on the other hand, are more expensive and have an abrupt saturation characteristic with the induc- tance dropping sharply when the peak design current is exceeded. nevertheless, they are pre- ferred at high switching frequencies because they present very low core loss and the design only needs to prevent saturation. the power dissipated in the inductor is equal to the sum of the core and copper losses. to mini- mize copper losses, the winding resistance needs to be minimized, but this usually comes at the expense of a larger inductor. core losses have a more significant contribution at low output cur- rent where the copper losses are at a minimum, and can typically be neglected at higher output currents where the copper losses dominate. core loss information is usually available from the magnetic vendor. the copper loss in the inductor can be calculated using the following equation: winding rms l cu l r i p 2 ) ( ) ( = where i l(rms) is the rms inductor current that can be calculated as follows: i l(rms) = i out(max) 1 + 1 ( i pp ) 2 3 i out(max) output capacitor selection the required esr (equivalent series resis- tance) and capacitance drive the selection of the type and quantity of the output capacitors. the esr must be small enough that both the resis- tive voltage deviation due to a step change in the load current and the output ripple voltage do not exceed the tolerance limits expected on the output voltage. during an output load transient, the output capacitor must supply all the addi- tional current demanded by the load until the sp6123 adjusts the inductor current to the new value. therefore the capacitance must be large enough so that the output voltage is held up while the inductor current ramps up or down to applications information
10 date: 9/13/04 sp6123 low voltage, synchronous step down pwm controller ?copyright 2004 sipex corporation the value corresponding to the new load current. additionally, the esr in the output capacitor causes a step in the output voltage equal to the esr value multiplied by the change in load current. because of the fast transient response provided by the sp6123 when exposed to output load transient, the output capacitor is typically chosen for esr , not for capacitance value. the output capacitor? esr, combined with the inductor ripple current, is typically the main con- tributor to output voltage ripple. the maximum allowable esr required to maintain a specified output voltage ripple can be calculated by: pp out esr i v r ? where: ? v out = peak to peak output voltage ripple i pp = peak to peak inductor ripple current the total output ripple is a combination of the esr and the output capacitance value and can be calculated as follows: ? v out = ( i pp (1 ?d) ) 2 + (i pp r esr ) 2 c out f s where: d = duty cycle equal to v out /v in c out = output capacitance value recommended capacitors that can be used ef- fectively in sp6123 applications are: low-esr aluminum electrolytic capacitors, os-con ca- pacitors that provide a very high performance/ size ratio for electrolytic capacitors and low- esr tantalum capacitors. avx tps series and kemet t510 surface mount capacitors are popu- lar tantalum capacitors that work well in sp6123 applications. poscap from sanyo is a solid electrolytic chip capacitor that has low esr and high capacitance. for the same esr value, poscap has lower profile compared with tan- talum capacitor. panasonic offers the sp series of specialty poly- mer aluminum electrolytic surface mount ca- pacitors. these capacitors have a lower esr than tantalum capacitors, reducing the total num- ber of capacitance required for a given transient response. input capacitor selection the input capacitor should be selected for ripple current rating, capacitance and voltage rating. the input capacitor must meet the ripple current requirement imposed by the switching current. in continuous conduction mode, the source cur- rent of the high-side mosfet is approximately a square wave of duty cycle v out / v in . most of this current is supplied by the input bypass capacitors. the rms value of input capacitor current is determined at the maximum output current and under the assumption that the peak to peak inductor ripple current is low, it is given by: i cin(rms) = i out(max) d(1 - d) the worse case occurs when the duty cycle, d, is 50% and gives an rms current value equal to i out /2. select input capacitors with adequate ripple current rating to ensure reliable opera- tion. the power dissipated in the input capacitor is: ) ( 2 ) ( cin esr rms cin cin r i p = this can become a significant part of power losses in a converter and hurt the overall energy transfer efficiency. the input voltage ripple primarily depends on the input capacitor esr and capacitance. ignor- ing the inductor ripple current, the input voltage ripple can be determined by: 2 ) ( ) ( (max) ) ( in in s out in out max out cin esr out in v c f v v v i r i v ? + = ? the capacitor type suitable for the output ca- pacitors can also be used for the input capaci- tors. however, exercise extra caution when tan- talum capacitors are considered. tantalum ca- pacitors are known for catastrophic failure when exposed to surge current, and input capacitors are prone to such surge current when power supplies are connected ?ive?to low impedance applications information
11 date: 9/13/04 sp6123 low voltage, synchronous step down pwm controller ?copyright 2004 sipex corporation power sources. certain tantalum capacitors, such as a vx tps series, are surge tested. for generic tantalum capacitors, use 2:1 voltage derating to protect the input capacitors from surge fallout. mosfet selection the losses associated with mosfets can be divided into conduction and switching losses. conduction losses are related to the on resis- tance of mosfets, and increase with the load current. switching losses occur on each on/off transition when the mosfets experience both high current and voltage. since the bottom mosfet switches current from/to a paralleled diode (either its own body diode or an external schottky diode), the voltage across the mosfet is no more than 1v during switching transition. as a result, its switching losses are negligible. the switching losses are difficult to quantify due to all the variables affecting turn on/off time. however, making the assumption that the turn on and turn off transition times are equal, the transition time can be approximated by: t t = c iss v in , i g where c iss is the mosfet? input capacitance, or the sum of the gate-to-source capacitance, c gs , and the drain-to-gate capacitance, c gd . this parameter can be directly obtained from the mosfet? data sheet. i g is the gate drive current provided by the sp6123 (approximately 1a at v in =5v) and v in is the input supply voltage. therefore an approximate expression for the switching losses associated with the high side mosfet can be given as: p sh(max) = (v in(max) + v f )i out(max) t t f s , where t t is the switching transition time and v f is the free wheeling diode drop. switching losses need to be taken into account for high switching frequency, since they are directly proportional to switching frequency. the conduction losses associated with top and bottom mosfets are determined by p ch(max) = r ds(on) i out(max) 2 d p cl(max) = r ds(on) i out(max) 2 (1 - d), where: p ch(max) = conduction losses of the high side mosfet p cl(max) = conduction losses of the low side mosfet r ds(on) = drain to source on resistance. the total power losses of the top mosfet are the sum of switching and conduction losses. for synchronous buck converters of efficiency over 90%, allow no more than 4% power losses for high or low side mosfets. for input voltages of 3.3v and 5v, conduction losses often domi- nate switching losses. therefore, lowering the r ds(on) of the mosfets always improves effi- ciency even though it gives rise to higher switch- ing losses due to increased c iss . total gate charge is the charge required to turn the mosfets on and off under the specified operating conditions (v gs and v ds ). the gate charge is provided by the sp6123 gate drive circuitry. (at 500khz switching frequency, the gate charge is the dominant source of power dissipation in the sp6123). at low output levels, this power dissipation is noticeable as a reduc- tion in efficiency. the average current required to drive the high side and low side mosfets is: i g(av) = q gh f s + q gl f s , where q gh and q gl are the total charge for the high side and the low side mosfets respectively. considering that the gate charge current comes from the input supply voltage v in , the power dissipated in the sp6123 due to the gate drive is: p gate drive = v in i g(av) top and bottom mosfets experience unequal conduction losses if their on time is unequal. for applications running at large or small duty cycle, it makes sense to use different top and bottom mosfets. alternatively, parallel multiple mosfets to conduct large duty factor. r ds(on) varies greatly with the gate driver volt- age. the mosfet vendors often specify r ds(on) on multiple gate to source voltages (v gs ), as well as provide typical curve of r ds(on) versus applications information
12 date: 9/13/04 sp6123 low voltage, synchronous step down pwm controller ?copyright 2004 sipex corporation v gs . for 5v input, use the r ds(on) specified at 4.5v v gs . at the time of this publication, ven- dors, such as fairchild, siliconix and interna- tional rectifier, have started to specify r ds(on) at v gs less than 3v. this data is necessary for designs where the mosfets are driven with 3.3v. thermal calculation must be conducted to en- sure the mosfet can handle the maximum load current. the junction temperature of the mosfet, determined as follows, must stay below the maximum rating. ja mosfet a j r p t t (max) (max) (max ) + = , where t a(max) = maximum ambient temperature p mosfet(max) = maximum power dissipation of the mosfet r ja = junction to ambient thermal resistance. r ja of the device depends greatly on the board layout, as well as device package. significant thermal improvement can be achieved in the maxi- mum power dissipation through the proper design of copper mounting pads on the circuit board. for example, in a so-8 package, placing two 0.04 square inches copper pad directly under the pack- age, without occupying additional board space, can increase the maximum power dissipation from approximately 1 to 1.2w. for dpak package, enlarging the tap mounting pad to 1 square inches reduces the r ja from 96 c/w to 40 c/w. schottky diode selection when paralleled with the bottom mosfet, an optional schottky diode can improve efficiency and reduce noise. without this schottky diode, the body diode of the bottom mosfet con- ducts the current during the non-overlap time when both mosfets are turned off. unfortu- nately, the body diode has high forward voltage and reverse recovery problem. the reverse re- covery of the body diode causes additional switching noises when the diode turns off. the schottky diode alleviates this noise and addi- tionally improves efficiency thanks to its low forward voltage. the reverse voltage across the diode is equal to input voltage, and the diode must be able to handle the peak current equal to the maximum load current. the power dissipation of the schottky diode is determined by p diode = 2v f i out t nol f s where t nol = non-overlap time between g l and g h . v f = forward voltage of the schottky diode. sp6123 c2 c1 r1 comp figure 1. the rc network connected to the comp pin provides a pole and a zero to control loop. loop compensation design the goal of loop compensation is to manipulate loop frequency response such that its gain crosses over 0db at a slope of -20db/dec. the sp6123 has a transconductance error amplifier and re- quires the compensation network to be con- nected between the comp pin and ground, as shown in figure 1. the first step of compensation design is to pick the loop crossover frequency. high crossover frequency is desirable for fast transient response, but often jeopardize the system stability. cross- over frequency should be higher than the esr zero but less than 1/5 of the switching fre- quency. the esr zero is contributed by the esr associated with the output capacitors and can be determined by f z(esr) = 1 2 c out r esr crossover frequency of 20khz is a sound first try if low esr tantalum capacitors or poscaps are used at the output. the next step is to calcu- late the complex conjugate poles contributed by the lc output filter, applications information
13 date: 9/13/04 sp6123 low voltage, synchronous step down pwm controller ?copyright 2004 sipex corporation f p(lc) = 1 2 lc out the open loop gain of the whole system can be divided into the gain of the error amplifier, pwm modulator, buck converter, and feedback resistor divider. in order to crossover at the selected frequency f co , the gain of the error amplifier has to compensate for the attenuation caused by the rest of the loop at this frequency. in the rc network shown in figure 1, the product of r1 and the error amplifier transcond uctance determines this gain. therefore, r1 can be de- termined from the following equation that takes into account the typical error amplifier transconductance, reference voltage and pwm ramp built into the sp6123. r 1 = 2083v out f co f z (esr) v in f p(lc) 2 in figure 1, r1 and c1 provides a zero f z1 which needs to be placed at or below f p(lc) . if f z1 is made equal to f p(lc) for convenience, the value of c 1 can be calculated as c 1 = 1 2 f p(lc) r 1 the optional c 2 generates a pole f p1 with r 1 to cut down high frequency noise for reliable op- eration. this pole should be placed one decade higher than the crossover frequency to avoid erosion of phase margin. therefore, the value of the c 2 can be derived from c 2 = 1 20 f co r 1 figure 2 illustrates the overall loop frequency response and frequency of each pole and zero. to fine-tune the compensation, it is necessary to physically measure the frequency response us- ing a network analyzer. gain -20db/dec -40db/dec -20db/dec -20db/dec -20db/dec error amplifier loop f f f z1 f p(lc) f z(esr) f co f p1 figure 2. frequency response of a stable system and its error amplifier. d1 mbr0530 bst swn v cc v fb comp gh gl gnd r1 5.0 rz 20k cb 2.2 f sp6123a u1 cp 47pf q1 fds6890a c in 47 f ceramic r2 80k 1.6v/4a cbst 1 f l1 1 h c out 4x47 f ceramic r3 80k c1 330pf d2 stps2l25u cz 680pf 3v to 5.5v q1 fds6890a 1 2 3 4 8 7 6 5 figure 3. sp6123 buck converter design with ceramic output capacitors. applications information
14 date: 9/13/04 sp6123 low voltage, synchronous step down pwm controller ?copyright 2004 sipex corporation most electrolytic and tantalum capacitors come with adequate esr value to generate a zero below power supplies?crossover frequency. this is cru- cial to a stable close loop system. however, this same system can become unstable if ceramic out- put capacitors are used. the low esr associated with ceramic capacitors can push the esr zero above the crossover frequency and often higher than 1mhz. in this case, type iii compensation is required to provide additional low frequency zero for adequate phase margin and thus stable operation. the design of type iii compensation using sp6123 transconductance error amplifier is quite straightforward. first, the resonant frequency of the lc output filter could be derived from f r = 1 = 11.6khz 2 l 1 c out the values and references used in all the calcula- tions agree with the schematic shown in figure 3. select values of r2, c1, r z and c z to place two zeros below or equal to the lc resonant fre- quency. those two zeros are located at: f z1 = 1 = 6khz 2 r 2 c 1 f z2 = 1 = 11.7khz 2 r z c z there is low frequency pole determined by both the error amplifier gain and feedback gain. it occurs at f p1 = 1 = 3.25hz 2 (r 2 // r 3 )c z g m r out in sp6123, g m (error amplifier transconductance) and r out (error amplifier output impedance) are specified at 0.6ms and 3m ? , respectively. for frequencies above the second zero f z2 , the feedback gain rises at 20db/dec and is equal to a fb = 2 fr z c 1 however, the error amplifier gain a ea declines at -20db/dec due to c p . a ea = g m 2 fc p when a fb is less than a ea , the compensated error amplifier gain is dominated by a fb . as a result, it shows up as a positive 20db/dec slope. however, when the rising a fb crosses the fall- ing a ea at one particular frequency, the com- pensated error amplifier gain is now solely de- termined by a ea . therefore, the 20db/dec slope is converted to a -20db/dec slope, and the bode plot demonstrates a double pole at this fre- quency which is equal to f p2 = 1gm = 221khz 2 c p c 1 r z select c p such that f p2 is located at least a decade higher than the crossover frequency. as shown in figure 4, this type iii compensation generates a close loop system with 50 degree phase margin and crossover frequency at 20khz. this ensures a stable regulated power supply with tight dc regulation and fast transient response. figure 4. bode plot for schematic shown in figure 3. v in = 3.3v and v out = 1.6v, no load. -100 10hz 100hz 100hz 1.0khz 10khz 1.0mhz 10mhz gain phase frequency 200 100 0 -200 applications information
15 date: 9/13/04 sp6123 low voltage, synchronous step down pwm controller ?copyright 2004 sipex corporation figure 5. a voltage divider connected to the v fb pin programs the output voltage. v fb v out sp6123 r1 r2 overcurrent protection over current protection on the sp6123 is imple- mented through detection of an excess voltage condition across the high side switch during conduction. this is typically referred to as high side r ds(on) detection. by using the r ds(on) of q1 to measure the output current, the current limit circuit eliminates the sense resistor that would otherwise be required and the corre- sponding loss associated with it. this improves the overall efficiency and reduces the number of components in the power path benefiting size and cost. r ds(on) sensing is by default inaccu- rate and is primarily meant to protect the power supply during a fault condition. the overcurrent trip point will vary from unit to unit as the r ds(on) of mosfet varies. the sp6123 pro- vides a built-in 200mv threshold between the v cc and swn pins. the overcurrent threshold can be calculated as i max = 200mv r ds(on) to ensure accurate current sensing, the v cc pin should be connected directly to the drain of the high side mosfet. a rc filter on the v cc pin is not recommended because it would artifi- cially alter the current signal and reduce the overcurrent threshold from the value given by the equation. output voltage program as shown in figure 5, the voltage divider con- necting to the v fb pin programs the output voltage according to v out = 0.8(1 + r 1 ) r 2 where 0.8v is the internal reference voltage. select r2 in the range of 10k to 100k, and r1 can be calculated using r 1 = r 2 (v out ? 0.8) 0.8 applications information
16 date: 9/13/04 sp6123 low voltage, synchronous step down pwm controller ?copyright 2004 sipex corporation pcb layout plays a critical role in proper func- tion of the converters and emi control. in switch mode power supplies, loops carrying high di/dt give rise to emi and ground bounces. the goal of layout optimization is to identify these loops and minimize them. it is also crucial on how to connect the controller ground such that its op- eration is not affected by noise. the following guideline should be followed to ensure proper operation. 1. a ground plane is recommended for minimiz- ing noises, copper losses and maximizing heat dissipation. 2. begin the layout by placing the power compo- nents first. orient the power circuitry to achieve a clean power flow path. if possible make all the connections on one side of the pcb with wide, copper filled areas. 3. connect the ground of feedback divider and compensation components directly to the gnd pin of the ic using a dedicated ground trace. then connect this pin as close as possible to the ground of the output capacitor. 4. the v cc bypass capacitor should be right next to the v cc and gnd pins. 5. the trace connecting the feedback resistors to the output should be short, direct and far away from the switch node, and switching compo- nents. 6. minimize the trace between g h /g l and the gates of the mosfets to reduce the impedance driving the mosfets. this is especially impor- tant for the bottom mosfet that tends to turn on through its miller capacitor when the switch node swings high. 7. minimize the loop composed of input capaci- tors, top/bottom mosfets and schottky diode. this loop carries high di/dt current. also in- crease the trace width to reduce copper losses. 8. maximize the trace width of the loop connect- ing the inductor, output capacitors, schottky diode and bottom mosfet. layout guideline
17 date: 9/13/04 sp6123 low voltage, synchronous step down pwm controller ?copyright 2004 sipex corporation see view c a a2 a1 seating plane side view to p view 8 pin nsoic p ackage: c with plating base metal b contact area 1 1.65 dimensions minimum/maximum (mm) 8 pin nsoic (jedec ms-012, aa - variation) common height dimension a a1 a2 b c l e e1 e l2 l1 1.35 4.90 bsc 0.40 0.31 0.51 symbol min nom max 0.10 - 0.25 d 1.75 1.25 0.17 0.25 6.00 bsc 3.90 bsc 1.27 bsc 1.27 1.04 ref 0.25 bsc 0 5 8 15 - - - - - - - (narrow refers to symbol e1) e e e/2 e1 index area (d/2 x e1/2) e1/2 d b 1 l1 l 1 1 seating plane gauge plane l2 view c package: 8 pin nsoic
18 date: 9/13/04 sp6123 low voltage, synchronous step down pwm controller ?copyright 2004 sipex corporation corporation analog excellence sipex corporation reserves the right to make changes to any products described herein. sipex does not assume any liability aris ing out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor t he rights of others. sipex corporation headquarters and sales office 233 south hillview drive milpitas, ca 95035 tel: (408) 934-7500 fax: (408) 935-7600 ordering information part number operating temperature range package type 500khz sp6123acn ............................................. 0?c to +70?c ........................................... 8-pin nsoic sp6123acn/tr ....................................... 0?c to +70?c ........................................... 8-pin nsoic 300khz sp6123cn ............................................... 0?c to +70?c ........................................... 8-pin nsoic sp6123cn/tr ......................................... 0?c to +70?c .......................................... 8-pin nsoic available in lead free packaging. to order add "-l" suffix to part number. example: sp6123cn/tr = standard; sp6123cn-l/tr = lead free /tr = tape and reel pack quantity is 2500 for nsoic.

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